ambrose
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usbreset
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usbreset/usbreset.kicad_pcb

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Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(kicad_pcb (version 20171130) (host pcbnew "(5.1.8-0-10_14)")
Initial custom footprints
2020-12-13 21:37:12 +08:00
(general
(thickness 1.6)
Improve GND routing
2021-01-10 17:54:03 +08:00
(drawings 11)
(tracks 533)
Initial custom footprints
2020-12-13 21:37:12 +08:00
(zones 0)
Route most connections
2020-12-19 17:42:18 +08:00
(modules 14)
(nets 22)
Initial custom footprints
2020-12-13 21:37:12 +08:00
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
Initial PCB layout
2020-12-14 00:17:44 +08:00
(last_trace_width 0.1524)
Route most connections
2020-12-19 17:42:18 +08:00
(trace_clearance 0.1524)
(zone_clearance 0.203)
Initial custom footprints
2020-12-13 21:37:12 +08:00
(zone_45_only no)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(trace_min 0.1524)
(via_size 0.381)
(via_drill 0.254)
(via_min_size 0.381)
(via_min_drill 0.254)
Initial custom footprints
2020-12-13 21:37:12 +08:00
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(segment_width 0.1524)
Initial custom footprints
2020-12-13 21:37:12 +08:00
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
Initial PCB layout
2020-12-14 00:17:44 +08:00
(net 1 "Net-(C1-Pad2)")
(net 2 VBUS)
Route most connections
2020-12-19 17:42:18 +08:00
(net 3 GND)
(net 4 SHIELD)
(net 5 /VBUS_SINK)
(net 6 "Net-(R1-Pad2)")
(net 7 "Net-(R2-Pad2)")
(net 8 /TX1+)
(net 9 /TX1-)
(net 10 /D+)
(net 11 /CC1)
(net 12 /SBU1)
(net 13 /D-)
(net 14 /RX2+)
(net 15 /RX2-)
(net 16 /TX2-)
(net 17 /RX1-)
(net 18 /CC2)
(net 19 /RX1+)
(net 20 /TX2+)
(net 21 /SBU2)
Initial custom footprints
2020-12-13 21:37:12 +08:00
(net_class Default "This is the default net class."
Route most connections
2020-12-19 17:42:18 +08:00
(clearance 0.1524)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(trace_width 0.1524)
(via_dia 0.381)
(via_drill 0.254)
Initial custom footprints
2020-12-13 21:37:12 +08:00
(uvia_dia 0.3)
(uvia_drill 0.1)
Route most connections
2020-12-19 17:42:18 +08:00
(add_net /CC1)
(add_net /CC2)
(add_net /D+)
(add_net /D-)
(add_net /RX1+)
(add_net /RX1-)
(add_net /RX2+)
(add_net /RX2-)
(add_net /SBU1)
(add_net /SBU2)
(add_net /TX1+)
(add_net /TX1-)
(add_net /TX2+)
(add_net /TX2-)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(add_net "Net-(C1-Pad2)")
(add_net "Net-(R1-Pad2)")
(add_net "Net-(R2-Pad2)")
Initial custom footprints
2020-12-13 21:37:12 +08:00
)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(net_class Power ""
More tweaks
2020-12-14 00:36:31 +08:00
(clearance 0.16)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(trace_width 0.2032)
(via_dia 0.508)
(via_drill 0.3302)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /VBUS_SINK)
(add_net GND)
(add_net VBUS)
)
Route most connections
2020-12-19 17:42:18 +08:00
(net_class Shield ""
(clearance 0.16)
(trace_width 0.254)
(via_dia 0.508)
(via_drill 0.3302)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net SHIELD)
)
(module Connector_USB-Custom:USB_C_Receptacle_Amphenol_10137065 (layer B.Cu) (tedit 5FD6293B) (tstamp 5FDDFD5D)
(at 153.375 94.488)
(path /5F1528AF)
(attr smd)
(fp_text reference J1 (at 0 -1 180) (layer B.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror))
)
(fp_text value USB_C_PowerSource (at 0 7 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 4.95 3.8) (end -4.95 3.8) (layer Cmts.User) (width 0.05))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 4.95 4.6) (end -4.95 4.6) (layer Cmts.User) (width 0.05))
(fp_line (start 4.95 5.35) (end -4.95 5.35) (layer Cmts.User) (width 0.05))
(fp_line (start -3.9 3.5) (end 3.9 3.5) (layer B.SilkS) (width 0.12))
(fp_line (start 3.9 3.5) (end 3.9 -1.75) (layer B.SilkS) (width 0.12))
(fp_line (start 3.9 -1.75) (end -3.9 -1.75) (layer B.SilkS) (width 0.12))
(fp_line (start -3.9 -1.75) (end -3.9 3.5) (layer B.SilkS) (width 0.12))
(fp_line (start -4.7 3.1) (end 4.4 3.1) (layer Cmts.User) (width 0.12))
(fp_line (start -3.6 5.4) (end -3.6 -2.4) (layer Cmts.User) (width 0.12))
(fp_line (start 4.95 6.25) (end -4.95 6.25) (layer Cmts.User) (width 0.05))
Route most connections
2020-12-19 17:42:18 +08:00
(pad S1 thru_hole roundrect (at -4 4.5) (size 1.65 1.1) (drill oval 1.25 0.7 (offset -0.1 0)) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad S1 thru_hole roundrect (at 4.32 5.1) (size 1.3 2.3) (drill oval 0.7 1.9) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad S1 thru_hole roundrect (at -4.33 5.1) (size 1.3 2.3) (drill oval 0.7 1.9) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad "" np_thru_hole roundrect (at 3.6 3.165) (size 0.85 0.5) (drill oval 0.85 0.5) (layers *.Cu *.Mask) (roundrect_rratio 0.5))
(pad "" np_thru_hole circle (at -3.6 3.1) (size 0.6 0.6) (drill 0.6) (layers *.Cu *.Mask))
(pad S1 thru_hole roundrect (at 4.32 0) (size 1.3 2.6) (drill oval 0.7 2) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad S1 thru_hole roundrect (at -4.32 0) (size 1.3 2.6) (drill oval 0.7 2) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad S1 thru_hole roundrect (at 4 4.5) (size 1.65 1.1) (drill oval 1.25 0.7 (offset 0.1 0)) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad A1 smd rect (at -2.625 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad A2 smd rect (at -2.125 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 8 /TX1+))
(pad A3 smd rect (at -1.625 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 9 /TX1-))
(pad A6 smd rect (at -0.125 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 10 /D+))
(pad A5 smd rect (at -0.625 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 11 /CC1))
(pad A4 smd rect (at -1.125 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 2 VBUS))
(pad A9 smd rect (at 1.375 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 2 VBUS))
(pad A12 smd rect (at 2.875 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad A8 smd rect (at 0.875 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 12 /SBU1))
(pad A7 smd rect (at 0.375 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 13 /D-))
(pad A11 smd rect (at 2.375 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 14 /RX2+))
(pad A10 smd rect (at 1.875 5.8) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 15 /RX2-))
(pad B3 smd rect (at 1.625 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 16 /TX2-))
(pad B10 smd rect (at -1.875 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 17 /RX1-))
(pad B5 smd rect (at 0.625 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 18 /CC2))
(pad B7 smd rect (at -0.375 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 13 /D-))
(pad B11 smd rect (at -2.375 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 19 /RX1+))
(pad B1 smd rect (at 2.625 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad B12 smd rect (at -2.875 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad B6 smd rect (at 0.125 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 10 /D+))
(pad B2 smd rect (at 2.125 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 20 /TX2+))
(pad B8 smd rect (at -0.875 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 21 /SBU2))
(pad B4 smd rect (at 1.125 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 2 VBUS))
(pad B9 smd rect (at -1.375 4.2) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 2 VBUS))
(model ${KIPRJMOD}/library/Connector_USB.3dshapes/USB_C_Receptacle_Amphenol_10137065.stp
(offset (xyz -4.15 -2 -0.6))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(module Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder (layer F.Cu) (tedit 5B301BBD) (tstamp 5FDDFAB0)
Route most connections
2020-12-19 17:42:18 +08:00
(at 160.796 94.488)
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5FEEB297)
(attr smd)
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_text reference R5 (at 0 0) (layer Cmts.User)
(effects (font (size 0.5 0.5) (thickness 0.125)))
Route most connections
2020-12-19 17:42:18 +08:00
)
(fp_text value 0 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.171267 -0.51) (end 0.171267 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.171267 0.51) (end 0.171267 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.65 0.73) (end -1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 -0.73) (end 1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.65 -0.73) (end 1.65 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.65 0.73) (end -1.65 0.73) (layer F.CrtYd) (width 0.05))
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 2 smd roundrect (at 0.875 0) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GND))
(pad 1 smd roundrect (at -0.875 0) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 SHIELD))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer B.Cu) (tedit 5FDDA99D) (tstamp 5FDDCE33)
(at 169.25 96.52 90)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x02 2.54mm single row")
(path /5FE36070)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference SW3 (at 0 2.33 -90) (layer Cmts.User)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text value SW_Push (at 0 -4.87 -90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Initial PCB layout
2020-12-14 00:17:44 +08:00
)
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -3.81) (end -1.27 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -3.81) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.8 1.8) (end -1.8 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -4.35) (end 1.8 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -4.35) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text user %R (at 0 -1.27 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Initial PCB layout
2020-12-14 00:17:44 +08:00
)
Route most connections
2020-12-19 17:42:18 +08:00
(pad 2 thru_hole oval (at 0 -2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(net 1 "Net-(C1-Pad2)"))
Route most connections
2020-12-19 17:42:18 +08:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 7 "Net-(R2-Pad2)"))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Improve GND routing
2021-01-10 17:54:03 +08:00
(module Connector_USB-Custom:USB_A_Receptacle_Amphenol_10117835 (layer B.Cu) (tedit 5FD6207C) (tstamp 5FFABDA9)
Route most connections
2020-12-19 17:42:18 +08:00
(at 139.446 102.87 90)
(path /5FD908A9)
(fp_text reference J4 (at 0 3.556 -90) (layer B.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror))
)
(fp_text value USB3_A_Receptacle (at 0 9.525 -90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -8.2 -8.6) (end -8.2 8.6) (layer B.CrtYd) (width 0.15))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 8.2 -8.6) (end -8.2 -8.6) (layer B.CrtYd) (width 0.15))
(fp_line (start 8.2 8.6) (end 8.2 -8.6) (layer B.CrtYd) (width 0.15))
(fp_line (start -8.2 8.6) (end 8.2 8.6) (layer B.CrtYd) (width 0.15))
(fp_line (start -7.94 -8.35) (end -7.94 8.35) (layer B.SilkS) (width 0.15))
(fp_line (start 7.94 -8.35) (end -7.94 -8.35) (layer B.SilkS) (width 0.15))
(fp_line (start 7.94 8.35) (end 7.94 -8.35) (layer B.SilkS) (width 0.15))
(fp_line (start -7.94 8.35) (end 7.94 8.35) (layer B.SilkS) (width 0.15))
Route most connections
2020-12-19 17:42:18 +08:00
(pad 1 thru_hole rect (at -3.5 5.43 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 5 /VBUS_SINK))
(pad 2 thru_hole circle (at -1 5.43 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 13 /D-))
(pad 4 thru_hole circle (at 3.5 5.43 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 3 GND))
(pad 3 thru_hole circle (at 1 5.43 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 10 /D+))
(pad 5 thru_hole circle (at 4 6.93 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 17 /RX1-))
(pad 6 thru_hole circle (at 2 6.93 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 19 /RX1+))
(pad 7 thru_hole circle (at 0 6.93 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 3 GND))
(pad 8 thru_hole circle (at -2 6.93 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 9 /TX1-))
(pad 9 thru_hole circle (at -4 6.93 90) (size 1.208 1.208) (drill 0.7) (layers *.Cu *.Mask)
(net 8 /TX1+))
(pad 10 thru_hole circle (at -6.57 3.43 90) (size 2.7 2.7) (drill 2.3) (layers *.Cu *.Mask)
(net 4 SHIELD))
(pad 10 thru_hole circle (at 6.57 3.43 90) (size 2.7 2.7) (drill 2.3) (layers *.Cu *.Mask)
(net 4 SHIELD))
(model ${KIPRJMOD}/library/Connector_USB.3dshapes/USB_A_Receptacle_Amphenol_10117835.stp
(offset (xyz 0 7.6 6.6))
(scale (xyz 1 1 1))
(rotate (xyz 180 0 0))
)
)
(module Button_Switch_SMD:SW_Push_1P1T_NO_CK_KSC7xxJ (layer B.Cu) (tedit 5C63FE2A) (tstamp 5FDDC43F)
(at 167.894 102.87 90)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "CK components KSC7 tactile switch https://www.ckswitches.com/media/1973/ksc7.pdf")
(tags "tactile switch ksc7")
(path /5F186D85)
(attr smd)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference SW2 (at 0 0 90) (layer B.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror))
Initial PCB layout
2020-12-14 00:17:44 +08:00
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text value SW_Push (at 0 4.23 90) (layer B.Fab)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start -3.1 3.1) (end 3.1 3.1) (layer B.Fab) (width 0.1))
(fp_line (start 3.1 3.1) (end 3.1 -3.1) (layer B.Fab) (width 0.1))
(fp_line (start 3.1 -3.1) (end -3.1 -3.1) (layer B.Fab) (width 0.1))
(fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer B.Fab) (width 0.1))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(fp_line (start -4.55 3.35) (end 4.55 3.35) (layer B.CrtYd) (width 0.05))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 4.55 3.35) (end 4.55 -3.35) (layer B.CrtYd) (width 0.05))
(fp_line (start 4.55 -3.35) (end -4.55 -3.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -4.55 -3.35) (end -4.55 3.35) (layer B.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 1.5 0) (layer B.Fab) (width 0.1))
(fp_line (start -3.21 -2.8) (end -3.21 -3.21) (layer B.SilkS) (width 0.12))
(fp_line (start -3.21 -3.21) (end 3.21 -3.21) (layer B.SilkS) (width 0.12))
(fp_line (start 3.21 -3.21) (end 3.21 -2.93) (layer B.SilkS) (width 0.12))
(fp_line (start 3.21 -1.2) (end 3.21 1.2) (layer B.SilkS) (width 0.12))
(fp_line (start 3.21 2.8) (end 3.21 3.21) (layer B.SilkS) (width 0.12))
(fp_line (start 3.21 3.21) (end -3.21 3.21) (layer B.SilkS) (width 0.12))
(fp_line (start -3.21 3.21) (end -3.21 2.8) (layer B.SilkS) (width 0.12))
(fp_line (start -3.21 1.2) (end -3.21 -1.2) (layer B.SilkS) (width 0.12))
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text user %R (at 0 0 90) (layer B.Fab)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Route most connections
2020-12-19 17:42:18 +08:00
(pad 2 smd rect (at 2.9 -2 90) (size 2.8 1) (layers B.Cu B.Paste B.Mask)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(net 1 "Net-(C1-Pad2)"))
Route most connections
2020-12-19 17:42:18 +08:00
(pad 2 smd rect (at -2.9 -2 90) (size 2.8 1) (layers B.Cu B.Paste B.Mask)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(net 1 "Net-(C1-Pad2)"))
Route most connections
2020-12-19 17:42:18 +08:00
(pad 1 smd rect (at 2.9 2 90) (size 2.8 1) (layers B.Cu B.Paste B.Mask)
(net 7 "Net-(R2-Pad2)"))
(pad 1 smd rect (at -2.9 2 90) (size 2.8 1) (layers B.Cu B.Paste B.Mask)
(net 7 "Net-(R2-Pad2)"))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KISYS3DMOD}/Button_Switch_SMD.3dshapes/SW_push_1P1T_NO_CK_KSC7xxJxxx.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Button_Switch_SMD-Custom:SW_SPDT_MSS3-V-T_R (layer F.Cu) (tedit 5FCE0B48) (tstamp 5FDE1EF6)
(at 164.592 109.982)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "Slide Switch, SPDT, Surface Mount. http://www.farnell.com/datasheets/1599440.pdf")
(path /5FD401C4)
(attr smd)
(fp_text reference SW1 (at -0.012 0.917) (layer F.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value EN_USBA (at 0 -3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_line (start -3 1.5) (end 3 1.5) (layer F.SilkS) (width 0.12))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 3.4 -0.5) (end 3.4 0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -3.4 -0.5) (end -3.4 0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -2.7 -1.4) (end -3 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 0.3 -1.4) (end -1.8 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 1.4 -1.4) (end 1.5 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 1.3 -1.4) (end 1.4 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 1.2 -1.4) (end 1.3 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 1.8 -1.4) (end 1.2 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 2.7 -1.4) (end 3 -1.4) (layer F.SilkS) (width 0.12))
(fp_line (start 1.5 1.6) (end 4.3 1.6) (layer F.CrtYd) (width 0.12))
(fp_line (start 1.5 3.2) (end 1.5 1.6) (layer F.CrtYd) (width 0.12))
(fp_line (start -1.5 3.2) (end 1.5 3.2) (layer F.CrtYd) (width 0.12))
(fp_line (start -1.5 1.6) (end -1.5 3.2) (layer F.CrtYd) (width 0.12))
(fp_line (start -4.3 1.6) (end -1.5 1.6) (layer F.CrtYd) (width 0.12))
(fp_line (start 4.3 1.6) (end 4.3 -2.6) (layer F.CrtYd) (width 0.12))
(fp_line (start -4.3 -2.6) (end -4.3 1.6) (layer F.CrtYd) (width 0.12))
(fp_line (start 4.3 -2.6) (end -4.3 -2.6) (layer F.CrtYd) (width 0.12))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(pad "" smd rect (at 3.65 -1.05) (size 1 0.8) (layers F.Cu F.Paste F.Mask))
Route most connections
2020-12-19 17:42:18 +08:00
(pad "" smd rect (at 3.65 1.05) (size 1 0.8) (layers F.Cu F.Paste F.Mask))
(pad "" np_thru_hole circle (at 1.5 0) (size 0.9 0.9) (drill 0.9) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -1.5 0) (size 0.9 0.9) (drill 0.9) (layers *.Cu *.Mask))
(pad 3 smd rect (at 2.25 -1.75) (size 0.7 1.5) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 0.75 -1.75) (size 0.7 1.5) (layers F.Cu F.Paste F.Mask)
(net 6 "Net-(R1-Pad2)"))
(pad 1 smd rect (at -2.25 -1.75) (size 0.7 1.5) (layers F.Cu F.Paste F.Mask)
(net 11 /CC1))
(pad "" smd rect (at -3.65 -1.05) (size 1 0.8) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at -3.65 1.05) (size 1 0.8) (layers F.Cu F.Paste F.Mask))
Initial PCB layout
2020-12-14 00:17:44 +08:00
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder (layer F.Cu) (tedit 5B301BBD) (tstamp 5FDE25E3)
(at 165.862 99.568 270)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5F197CA2)
(attr smd)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference R4 (at 0 0 90) (layer Cmts.User)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value 1.5M (at 0 1.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
More tweaks
2020-12-14 00:36:31 +08:00
(fp_line (start 1.65 0.73) (end -1.65 0.73) (layer F.CrtYd) (width 0.05))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 1.65 -0.73) (end 1.65 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 -0.73) (end 1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 0.73) (end -1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.171267 0.51) (end 0.171267 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.171267 -0.51) (end 0.171267 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.875 0 270) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 VBUS))
More tweaks
2020-12-14 00:36:31 +08:00
(pad 2 smd roundrect (at 0.875 0 270) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 1 "Net-(C1-Pad2)"))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder (layer F.Cu) (tedit 5B301BBD) (tstamp 5FDE23A5)
(at 168.388 100.33)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5F1CDC44)
(attr smd)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference R3 (at 0.014 0) (layer Cmts.User)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text value 1M (at 0 1.43) (layer F.Fab)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 1 1) (thickness 0.15)))
)
More tweaks
2020-12-14 00:36:31 +08:00
(fp_line (start 1.65 0.73) (end -1.65 0.73) (layer F.CrtYd) (width 0.05))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 1.65 -0.73) (end 1.65 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 -0.73) (end 1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 0.73) (end -1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.171267 0.51) (end 0.171267 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.171267 -0.51) (end 0.171267 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text user %R (at 0 0) (layer F.Fab)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
Route most connections
2020-12-19 17:42:18 +08:00
(pad 1 smd roundrect (at -0.875 0) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(net 1 "Net-(C1-Pad2)"))
Route most connections
2020-12-19 17:42:18 +08:00
(pad 2 smd roundrect (at 0.875 0) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GND))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder (layer F.Cu) (tedit 5B301BBD) (tstamp 5FDE1EB8)
(at 168.402 98.806)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5F199070)
(attr smd)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference R2 (at 0 0) (layer Cmts.User)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text value 40k (at 0 1.43) (layer F.Fab)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 1 1) (thickness 0.15)))
)
More tweaks
2020-12-14 00:36:31 +08:00
(fp_line (start 1.65 0.73) (end -1.65 0.73) (layer F.CrtYd) (width 0.05))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 1.65 -0.73) (end 1.65 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 -0.73) (end 1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 0.73) (end -1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.171267 0.51) (end 0.171267 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.171267 -0.51) (end 0.171267 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text user %R (at 0 0) (layer F.Fab)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
Route most connections
2020-12-19 17:42:18 +08:00
(pad 1 smd roundrect (at -0.875 0) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(net 2 VBUS))
Route most connections
2020-12-19 17:42:18 +08:00
(pad 2 smd roundrect (at 0.875 0) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 7 "Net-(R2-Pad2)"))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Resistor_SMD:R_0603_1608Metric_Pad1.05x0.95mm_HandSolder (layer F.Cu) (tedit 5B301BBD) (tstamp 5FDE1F42)
(at 164.733 106.426)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5FD50642)
(attr smd)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference R1 (at -0.268 1.016) (layer Cmts.User)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value 5.1k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_line (start 1.65 0.73) (end -1.65 0.73) (layer F.CrtYd) (width 0.05))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 1.65 -0.73) (end 1.65 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 -0.73) (end 1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 0.73) (end -1.65 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.171267 0.51) (end 0.171267 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.171267 -0.51) (end 0.171267 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.875 0) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
Route most connections
2020-12-19 17:42:18 +08:00
(net 3 GND))
(pad 2 smd roundrect (at 0.875 0) (size 1.05 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 6 "Net-(R1-Pad2)"))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Package_TO_SOT_SMD:SOT-23 (layer F.Cu) (tedit 5A02FF57) (tstamp 5FDE1E20)
(at 161.798 99.568 180)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "SOT-23, Standard")
(tags SOT-23)
(path /5F1BFDC6)
(attr smd)
(fp_text reference Q1 (at 0 0.066 90) (layer F.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value SI2393DS (at 0 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 0.76 1.58) (end -0.7 1.58) (layer F.SilkS) (width 0.12))
(fp_line (start 0.76 -1.58) (end -1.4 -1.58) (layer F.SilkS) (width 0.12))
(fp_line (start -1.7 1.75) (end -1.7 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 1.75) (end -1.7 1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -1.75) (end 1.7 1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -1.75) (end 1.7 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.76 -1.58) (end 0.76 -0.65) (layer F.SilkS) (width 0.12))
(fp_line (start 0.76 1.58) (end 0.76 0.65) (layer F.SilkS) (width 0.12))
(fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1))
(fp_line (start 0.7 -1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.95) (end -0.15 -1.52) (layer F.Fab) (width 0.1))
(fp_line (start -0.15 -1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.95) (end -0.7 1.5) (layer F.Fab) (width 0.1))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.075)))
)
(pad 1 smd rect (at -1 -0.95 180) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
(net 1 "Net-(C1-Pad2)"))
More tweaks
2020-12-14 00:36:31 +08:00
(pad 2 smd rect (at -1 0.95 180) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
(net 2 VBUS))
(pad 3 smd rect (at 1 0 180) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
Route most connections
2020-12-19 17:42:18 +08:00
(net 5 /VBUS_SINK))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-23.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Connector_USB-Custom:USB_A_Plug_Amphenol_GSB3164x1CEU (layer B.Cu) (tedit 5FD63F16) (tstamp 5FDD96B0)
(at 177.8 102.87 270)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(path /5FDACC9B)
(attr smd)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference J3 (at 0 -1.85 90) (layer B.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror))
Initial PCB layout
2020-12-14 00:17:44 +08:00
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text value USB3_A_Plug (at 0 5.08 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Initial PCB layout
2020-12-14 00:17:44 +08:00
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_line (start -6.5 -2.55) (end 6.5 -2.55) (layer B.CrtYd) (width 0.12))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 6.5 -2.55) (end 6.5 4.25) (layer B.CrtYd) (width 0.12))
(fp_line (start 6.5 4.25) (end -6.5 4.25) (layer B.CrtYd) (width 0.12))
(fp_line (start -6.5 4.25) (end -6.5 -2.55) (layer B.CrtYd) (width 0.12))
(fp_line (start -5.85 -2.55) (end -5.85 -2.05) (layer B.SilkS) (width 0.12))
(fp_line (start 5.85 -2.55) (end 5.85 -2.05) (layer B.SilkS) (width 0.12))
(fp_line (start -5 1.4) (end 5 1.4) (layer B.SilkS) (width 0.12))
(fp_line (start -5.85 -2.55) (end 5.85 -2.55) (layer B.SilkS) (width 0.12))
Route most connections
2020-12-19 17:42:18 +08:00
(pad "" np_thru_hole circle (at -2.25 0 270) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 2.25 0 270) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask))
(pad 2 smd rect (at 1 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
(net 13 /D-))
(pad 1 smd rect (at 3 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(net 2 VBUS))
Route most connections
2020-12-19 17:42:18 +08:00
(pad 8 smd rect (at 2 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
(net 9 /TX1-))
(pad 9 smd rect (at 4 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
(net 8 /TX1+))
(pad 5 smd rect (at -4 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
(net 17 /RX1-))
(pad 4 smd rect (at -3 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad 6 smd rect (at -2 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
(net 19 /RX1+))
(pad 3 smd rect (at -1 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
(net 10 /D+))
(pad 7 smd rect (at 0 2.85 270) (size 0.8 2.78) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad 10 thru_hole oval (at 5.85 0 270) (size 1.3 3.3) (drill oval 0.9 2.9) (layers *.Cu *.Mask)
(net 4 SHIELD))
(pad 10 thru_hole oval (at -5.85 0 270) (size 1.3 3.3) (drill oval 0.9 2.9) (layers *.Cu *.Mask)
(net 4 SHIELD))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KIPRJMOD}/library/Connector_USB.3dshapes/USB_A_Plug_Amphenol_GSB3164x1CEU.stp
(offset (xyz 0.1 -8.1 1.5))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 180))
)
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Connector_USB-Custom:USB_C_Receptacle_Amphenol_10137065 (layer B.Cu) (tedit 5FD6293B) (tstamp 5FDDE55B)
(at 153.375 111.25 180)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(path /5F157FC7)
(attr smd)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference J2 (at 0 -1) (layer B.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror))
Initial PCB layout
2020-12-14 00:17:44 +08:00
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text value USB_C_PowerSink (at 0 7) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Initial PCB layout
2020-12-14 00:17:44 +08:00
)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_line (start 4.95 6.25) (end -4.95 6.25) (layer Cmts.User) (width 0.05))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start -3.6 5.4) (end -3.6 -2.4) (layer Cmts.User) (width 0.12))
(fp_line (start -4.7 3.1) (end 4.4 3.1) (layer Cmts.User) (width 0.12))
(fp_line (start -3.9 -1.75) (end -3.9 3.5) (layer B.SilkS) (width 0.12))
(fp_line (start 3.9 -1.75) (end -3.9 -1.75) (layer B.SilkS) (width 0.12))
(fp_line (start 3.9 3.5) (end 3.9 -1.75) (layer B.SilkS) (width 0.12))
(fp_line (start -3.9 3.5) (end 3.9 3.5) (layer B.SilkS) (width 0.12))
(fp_line (start 4.95 5.35) (end -4.95 5.35) (layer Cmts.User) (width 0.05))
(fp_line (start 4.95 4.6) (end -4.95 4.6) (layer Cmts.User) (width 0.05))
(fp_line (start 4.95 3.8) (end -4.95 3.8) (layer Cmts.User) (width 0.05))
Route most connections
2020-12-19 17:42:18 +08:00
(pad B9 smd rect (at -1.375 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 5 /VBUS_SINK))
(pad B4 smd rect (at 1.125 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 5 /VBUS_SINK))
(pad B8 smd rect (at -0.875 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 12 /SBU1))
(pad B2 smd rect (at 2.125 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 8 /TX1+))
(pad B6 smd rect (at 0.125 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 10 /D+))
(pad B12 smd rect (at -2.875 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad B1 smd rect (at 2.625 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad B11 smd rect (at -2.375 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 14 /RX2+))
(pad B7 smd rect (at -0.375 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 13 /D-))
(pad B5 smd rect (at 0.625 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 11 /CC1))
(pad B10 smd rect (at -1.875 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 15 /RX2-))
(pad B3 smd rect (at 1.625 4.2 180) (size 0.275 0.8) (layers B.Cu B.Paste B.Mask)
(net 9 /TX1-))
(pad A10 smd rect (at 1.875 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 17 /RX1-))
(pad A11 smd rect (at 2.375 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 19 /RX1+))
(pad A7 smd rect (at 0.375 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 13 /D-))
(pad A8 smd rect (at 0.875 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 21 /SBU2))
(pad A12 smd rect (at 2.875 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad A9 smd rect (at 1.375 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 5 /VBUS_SINK))
(pad A4 smd rect (at -1.125 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 5 /VBUS_SINK))
(pad A5 smd rect (at -0.625 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 18 /CC2))
(pad A6 smd rect (at -0.125 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 10 /D+))
(pad A3 smd rect (at -1.625 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 16 /TX2-))
(pad A2 smd rect (at -2.125 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 20 /TX2+))
(pad A1 smd rect (at -2.625 5.8 180) (size 0.275 0.9) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(pad S1 thru_hole roundrect (at 4 4.5 180) (size 1.65 1.1) (drill oval 1.25 0.7 (offset 0.1 0)) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad S1 thru_hole roundrect (at -4.32 0 180) (size 1.3 2.6) (drill oval 0.7 2) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad S1 thru_hole roundrect (at 4.32 0 180) (size 1.3 2.6) (drill oval 0.7 2) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad "" np_thru_hole circle (at -3.6 3.1 180) (size 0.6 0.6) (drill 0.6) (layers *.Cu *.Mask))
(pad "" np_thru_hole roundrect (at 3.6 3.165 180) (size 0.85 0.5) (drill oval 0.85 0.5) (layers *.Cu *.Mask) (roundrect_rratio 0.5))
(pad S1 thru_hole roundrect (at -4.33 5.1 180) (size 1.3 2.3) (drill oval 0.7 1.9) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad S1 thru_hole roundrect (at 4.32 5.1 180) (size 1.3 2.3) (drill oval 0.7 1.9) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
(pad S1 thru_hole roundrect (at -4 4.5 180) (size 1.65 1.1) (drill oval 1.25 0.7 (offset -0.1 0)) (layers *.Cu *.Mask) (roundrect_rratio 0.5)
(net 4 SHIELD))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KIPRJMOD}/library/Connector_USB.3dshapes/USB_C_Receptacle_Amphenol_10137065.stp
(offset (xyz -4.15 -2 -0.6))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
Route most connections
2020-12-19 17:42:18 +08:00
(module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5FDE1DEC)
(at 164.338 99.568 270)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags capacitor)
(path /5F18B248)
(attr smd)
Route most connections
2020-12-19 17:42:18 +08:00
(fp_text reference C1 (at 0 0 90) (layer Cmts.User)
Initial PCB layout
2020-12-14 00:17:44 +08:00
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value 2000pF (at 0 1.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
More tweaks
2020-12-14 00:36:31 +08:00
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 270) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 VBUS))
More tweaks
2020-12-14 00:36:31 +08:00
(pad 2 smd roundrect (at 0.7875 0 270) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 1 "Net-(C1-Pad2)"))
Initial PCB layout
2020-12-14 00:17:44 +08:00
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Improve GND routing
2021-01-10 17:54:03 +08:00
(gr_text "@serverwentdown\nusbreset v1" (at 172.55 102.9 90) (layer F.Mask) (tstamp 5FFAD669)
(effects (font (size 0.75 0.75) (thickness 0.1)))
)
Route most connections
2020-12-19 17:42:18 +08:00
(gr_text Source (at 153.416 93.98 180) (layer F.SilkS) (tstamp 5FDDCA3C)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text Sink (at 153.416 111.76) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_arc (start 143.51 110.49) (end 140.97 110.49) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 143.51 95.25) (end 143.51 92.71) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_line (start 177.8 113.03) (end 143.51 113.03) (layer Edge.Cuts) (width 0.05) (tstamp 5FDDB172))
(gr_arc (start 177.8 110.49) (end 177.8 113.03) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_line (start 180.34 95.25) (end 180.34 110.49) (layer Edge.Cuts) (width 0.05) (tstamp 5FDDC29E))
(gr_arc (start 177.8 95.25) (end 180.34 95.25) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_line (start 177.8 92.71) (end 143.51 92.71) (layer Edge.Cuts) (width 0.05) (tstamp 5FD6C775))
(gr_line (start 140.97 95.25) (end 140.97 110.49) (layer Edge.Cuts) (width 0.05) (tstamp 5FD6C7AB))
Initial PCB layout
2020-12-14 00:17:44 +08:00
Route most connections
2020-12-19 17:42:18 +08:00
(segment (start 164.1755 100.518) (end 164.338 100.3555) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 162.798 100.518) (end 164.1755 100.518) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 165.894 99.97) (end 165.894 98.838) (width 0.1524) (layer B.Cu) (net 1))
(segment (start 166.71 98.022) (end 166.71 96.52) (width 0.1524) (layer B.Cu) (net 1))
(segment (start 165.894 98.838) (end 166.71 98.022) (width 0.1524) (layer B.Cu) (net 1))
Improve GND routing
2021-01-10 17:54:03 +08:00
(via (at 165.862 104.661998) (size 0.381) (drill 0.254) (layers F.Cu B.Cu) (net 1))
Route most connections
2020-12-19 17:42:18 +08:00
(segment (start 165.894 105.77) (end 165.862 105.738) (width 0.1524) (layer B.Cu) (net 1))
Improve GND routing
2021-01-10 17:54:03 +08:00
(segment (start 165.862 105.738) (end 165.862 104.661998) (width 0.1524) (layer B.Cu) (net 1))
(via (at 165.862 100.961996) (size 0.381) (drill 0.254) (layers F.Cu B.Cu) (net 1))
(segment (start 165.862 104.661998) (end 165.862 100.961996) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 164.338 100.3555) (end 165.255504 100.3555) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 167.513 100.33) (end 166.493996 100.33) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 166.493996 100.33) (end 165.862 100.961996) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 165.255504 100.3555) (end 165.862 100.961996) (width 0.1524) (layer F.Cu) (net 1))
Route most connections
2020-12-19 17:42:18 +08:00
(segment (start 152.25 99.55) (end 152.25 100.288) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 152 99.3) (end 152.25 99.55) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 152 98.688) (end 152 99.3) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 154.5 99.3) (end 154.75 99.55) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 154.75 99.55) (end 154.75 100.288) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 154.5 98.688) (end 154.5 99.3) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 167.414 98.693) (end 167.527 98.806) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 165.862 98.693) (end 167.414 98.693) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 164.4255 98.693) (end 164.338 98.7805) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 165.862 98.693) (end 164.4255 98.693) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 164.1755 98.618) (end 164.338 98.7805) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 162.798 98.618) (end 164.1755 98.618) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 154.5 97.858) (end 154.5 98.688) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 153.924 97.282) (end 154.5 97.858) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 152.4 97.282) (end 153.924 97.282) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 152 97.682) (end 152.4 97.282) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 152 98.688) (end 152 97.682) (width 0.2032) (layer B.Cu) (net 2))
Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
(segment (start 162.798 98.618) (end 162.798 98.102) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 162.798 98.102) (end 165.8 95.1) (width 0.2032) (layer F.Cu) (net 2))
(via (at 174.95 105.87) (size 0.508) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 170.000882 95.1) (end 174.95 100.049118) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 174.95 100.049118) (end 174.95 105.87) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 161.38 97.2) (end 157.85 97.2) (width 0.2032) (layer F.Cu) (net 2))
Improve GND routing
2021-01-10 17:54:03 +08:00
(via (at 156.050002 97.29021) (size 0.508) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 156.304001 97.036211) (end 156.050002 97.29021) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 157.85 97.2) (end 157.686211 97.036211) (width 0.2032) (layer F.Cu) (net 2))
(segment (start 153.924 97.282) (end 156.041792 97.282) (width 0.2032) (layer B.Cu) (net 2))
(segment (start 157.686211 97.036211) (end 156.304001 97.036211) (width 0.2032) (layer F.Cu) (net 2))
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Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
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Improve GND routing
2021-01-10 17:54:03 +08:00
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Finish 1st routing pass, add 3D preview
2020-12-19 22:25:09 +08:00
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Improve GND routing
2021-01-10 17:54:03 +08:00
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